1. Field of the Invention
The present invention relates generally to a memory controller and a semiconductor memory device, and relates, for example, to a memory controller which includes an ECC (Error Correcting Code) circuit.
2. Description of the Related Art
There is known a page format of a memory card including a nonvolatile semiconductor memory as a main memory, the page format being configured such that only one redundant unit area, in which management information is written, can be secured in every page. In particular, in the case where the nonvolatile semiconductor is a multi-value memory, such a page format is adopted.
Assume now that the above-described page format was adopted and data was not fully written in the page, that is, the length of the data was less than a predetermined data length.
In this case, in order to write management information in a redundant unit data area, a memory controller, which controls the nonvolatile semiconductor memory, adds dummy data at one part of the format in which the management information is written. Thus, the data length of this part is set at a predetermined data length for generating a parity for error detection/correction (ECC). Thereafter, the memory controller inputs a data string of a predetermined data length, which includes the dummy data+management information, to an ECC core that is provided in the memory controller. Then, the memory controller generates an ECC parity from the data string of the predetermined data length. Subsequently, the data string including the dummy data, management information and ECC parity is sent to the nonvolatile semiconductor memory, and the data of the data string is written in the nonvolatile semiconductor memory.
However, the clear state of a page buffer, which is provided in the nonvolatile semiconductor memory, is “1”. Thus, the dummy data must be all set at “1”, and the ECC parity is generated from the data string of all “1” dummy data+management information.
As described above, the conventional memory controller executes input of all “1” dummy data to the ECC core, and generation of the ECC parity from the data string of all “1” dummy data+management information. Hence, a decrease in time that is needed for data transfer to the nonvolatile semiconductor memory is hindered.